1. Field of the Invention
The present invention relates to a synchronous semiconductor storage device, and specifically to a synchronous semiconductor storage device in which the amount of current consumed in a standby mode is reduced.
2. Description of the Related Art
In recent years, along with the increase in operation speed of microprocessors, etc., demand for semiconductor storage devices which operate at higher speed has been growing. A semiconductor storage device developed for the purpose of meeting such a demand is a synchronous semiconductor storage device that operates in a synchronous burst operation mode. In such a storage device, high speed readout of data is achieved in addition to the increase in speed for normal random access, although an access method is limited to some extent.
The synchronous burst operation mode used in a clock synchronous semiconductor storage device is a high speed access mode in which predetermined data rows are sequentially output in synchronization with a system clock signal. One example of a synchronous semiconductor storage device which operates in a synchronous burst operation mode include a synchronous DRAM (hereinafter, referred to as xe2x80x9cSDRAMxe2x80x9d).
FIG. 8 shows an exemplary structure of an input circuit used in an SDRAM. This input circuit includes an internal clock activation signal generation circuit 52 which receives a system clock signal CLK and a clock activation signal CKE and outputs an internal clock activation signal xcfx8651, and an internal clock signal generation circuit 53 which generates an internal clock signal clk_in based on the internal clock activation signal xcfx8651 and the system clock signal CLK.
FIG. 9 shows a structure of the internal clock activation signal generation circuit 52 which includes a pair of D-flip flop (D-FF) circuits 50 and 51 and an inverter INV50. The first D-FF circuit 50 receives a clock activation signal CKE at a data input terminal D, and a system clock signal CLK at a clock input terminal CK.
The first D-FF circuit 50 outputs a CKE latch output signal xcfx8650 from its output terminal Q to a data input terminal D of the second D-FF circuit 51. The second D-FF circuit 51 receives a system clock signal CLK at its clock terminal CK through the inverter INV50. The second D-FF circuit 51 outputs from its output terminal Q an internal clock activation signal xcfx8651 to the internal clock signal generation circuit 53.
FIG. 10 shows a structure of the internal clock signal generation circuit 53. The internal clock signal generation circuit 53 includes an NAND gate NAND54 and an inverter INV55. The NAND gate NAND54 receives the internal clock activation signal xcfx8651 from the internal clock activation signal generation circuit 52, and the system clock signal CLK. The inverter INV55 receives an output of the NAND gate NAND54. The internal clock signal generation circuit 53 outputs an output of the inverter INV55 as an internal clock signal clk_in.
Operations of the input circuit having the above structure are described with reference to a timing chart as shown in FIG. 11. Upon receiving the system clock signal CLK, the input circuit receives, at each rising edge of the pulse of the system clock signal CLK, a control signal and an address signal from outside in a time-division manner.
As shown in FIG. 11, the internal clock signal clk_in, which is used for receiving the control signal and the address signal, is controlled by the level of the clock activation signal CKE at each rising edge of the system clock signal CLK. Specifically, based on the level of the clock activation signal CKE at a rising edge of the system clock signal CLK, it is determined whether or not a pulse is generated as the internal clock signal clk_in in synchronization with a pulse of the system clock CLK in the subsequent clock cycle. For example, when the level of the clock activation signal CKE at a rising edge of the system clock signal CLK is a high level xe2x80x9cHxe2x80x9d, a pulse is generated as an internal clock signal clk_in in synchronization with a pulse of the system clock CLK in the subsequent clock cycle. When the level of the clock activation signal CKE at a rising edge of the system clock signal CLK is a low level xe2x80x9cLxe2x80x9d, a pulse of the internal clock signal clk_in is not generated in the subsequent clock cycle.
The generated internal clock signal clk_in is used as a synchronization signal in each of latch circuits 56 (FIG. 12) for latching an input address data signal and a control signal, etc., which are provided from outside. Each latch circuit 56 outputs the input address data signal and the control signal, etc., to the principal part of the semiconductor storage device in synchronization with the internal clock signal clk_in.
However, in a conventional internal clock activation signal generation circuit 52, since the level of the clock activation signal CKE must be referred to at each rising edge of the system clock signal CLK, a large amount of electric current is consumed by a clock buffer of the internal clock activation signal generation circuit 52 which receives the system clock signal CLK. That is, switching of logic gates such as the first D-FF circuit 50, the inverter INV5O, the NAND gate NAND54, etc., to which the system clock signal CLK is directly input, generates a discharge current due to a gate capacitance or a parasitic capacitance in a logic gate, etc., to which an output of a previous logic gate is supplied, in addition to the generation of a through-current. Thus, the amount of current consumed when the clock activation signal CKE is at a low level xe2x80x9cLxe2x80x9d and the semiconductor storage device is on standby cannot be reduced.
Especially when the frequency of the system clock signal CLK is increased, the current consumption is from about several hundreds of microamperes to about 1 mA. In a commonly-employed SDRAM, such an increase in current consumption is a significant problem.
Japanese Laid-Open Publication No. 7-177015 discloses a method for reducing the current consumption in the standby state of SDRAM. According to this method, when a first stage circuit, which receives external input signals used in the SDRAM except for the system clock signal CLK and the clock activation signal CKE, is on standby, power supply to the first stage circuit is stopped, whereby the current consumption is reduced.
However, such a method requires a level detection circuit for detecting the level of the clock activation signal CKE in order to detect the standby state, and it is required to incessantly supply the system clock signal CLK to the level detection circuit. Thus, as the frequency of the system clock signal CLK increases, the amount of current consumed by the level detection circuit increases.
Furthermore, Japanese Laid-Open Publication No. 11-16349 discloses a method for reducing the amount of current consumed when an internal operation of a storage device is on standby. According to this method, in the case where the clock activation signal CKE turns to a high level xe2x80x9cHxe2x80x9d and the internal operation is on standby, the internal clock signal is eliminated, whereby the current consumption is reduced.
However, according to such a method, in the case where the clock activation signal CKE is at a low level xe2x80x9cLxe2x80x9d and the internal operation is on standby, or in the case where a clock signal is adjusted to the operation frequency of an external system with which signals are exchanged, the current consumption cannot be reduced when the internal operation is in a clock suspend mode (which is an operation mode for memory access) by partially masking the clock signal so as to decrease the operation frequency.
Since a clock synchronous semiconductor storage device receives input signals at latch circuits in synchronization with rising edges of a system clock signal, the latch circuits each need to have received the system clock signal before or at the time of data input. Therefore, a conventional synchronous semiconductor storage device receives input data while an internal clock signal clk_in which has been generated by the internal clock signal generation circuit 53 (FIG. 10) is being incessantly input to the latch circuits; or receives input data such that, as described in Japanese Laid-Open Publication No. 11-16349, an internal clock signal clk_in is generated only when the data is input to the synchronous semiconductor storage device. However, in such a structure, the system clock signal which is input to a clock buffer of a level detection circuit for detecting the level of the clock activation signal CKE cannot be removed.
Thus, in the conventional synchronous semiconductor storage device, there are significant drawbacks in that a current of from about several hundreds of microamperes to about 1 mA is consumed even in a clock buffer portion of the level detection circuit for detecting the level of the clock activation signal CKE due to the variation of the system clock signal, and that the current consumption increases due to the increase in frequency of the system clock signal.
According to one aspect of the present invention, a synchronous semiconductor storage device includes: an internal clock activation signal generation circuit for generating an internal clock activation signal cke_c and a latch signal cke1 based on a system clock signal CLK and a clock activation signal CKE each having a series of pulses: a CKE latch clock control signal generation circuit for generating, based on the internal clock activation signal cke_c, the latch signal cke1, the system clock signal CLK, and the clock activation signal CKE, a CKE latch clock control signal cke_x which is controls activation/inactivation of a CKE latch clock signal; and an internal clock signal generation circuit for generating an internal clock signal clk_in based on the internal clock activation signal cke_c and the system clock signal CLK, wherein stored data corresponding to a plurality of external signals including a control signal and an address signal are transmitted in synchronization with the internal clock signal clk_in.
In one embodiment of the present invention, the internal clock activation signal generation circuit includes: a clock buffer for controlling an input of the system clock signal CLK based on the CKE latch clock control signal cke_x generated by the CKE latch clock control signal generation circuit; an inverter which receives an output from the clock buffer; and a CKE level hold circuit including serially connected three latch circuits, which generates the internal clock activation signal cke_c and the latch signal cke1 from the clock activation signal CKE or from a signal derived from the clock activation signal CKE based on an output of the inverter and the output of the clock buffer.
In another embodiment of the present invention, the internal clock signal generation circuit includes a clock buffer for controlling an input of the system clock signal CLK based on the internal clock activation signal cke_c generated by the internal clock activation signal generation circuit.
In still another embodiment of the present invention, the CKE latch clock control signal generation circuit includes: a standby state detection circuit for generating a control signal which inactivates the CKE latch clock control signal cke_x based on the internal clock activation signal cke_c and the latch signal cke1 generated by the internal clock activation signal generation circuit; a non-standby state detection circuit for generating a control signal which activates the CKE latch clock control signal cke_x, based on the system clock signal CLK and the clock activation signal CKE; a latch circuit which receives the control signal from the standby state detection circuit and the control signal from the non-standby state detection circuit.
In still another embodiment of the present invention, the level of the clock activation signal CKE is latched at a rising edge of the system clock signal CLK, by first and second latch circuits among the three latch circuits included in the CKE level hold circuit, based on the internal clock activation signal cke_c; and the latched level of the clock activation signal CKE is identical with a level of a signal which is held at a falling edge of the system clock signal CLK and output by a third latch circuit of the CKE level hold circuit.
In still another embodiment of the present invention, the CKE latch clock control signal cke_x generated by the CKE latch clock control signal generation circuit is activated by the control signal output from the non-standby state detection circuit and inactivated by the control signal output from the standby state detection circuit; and alternation between an active state and an inactive state is made in synchronization with a falling edge of the system clock signal CLK.
In still another embodiment of the present invention, the synchronous semiconductor storage device further including: a memory cell array including a plurality of memory cells arranged in a matrix; and a row select circuit for selecting, in response to an input address, a row in the memory cell array which corresponds to the input address, wherein memory cells in the selected row are sequentially accessed in a synchronous burst mode in synchronization with the internal clock signal clk_in.
Thus, the invention described herein makes possible the advantages of (1) providing a synchronous semiconductor storage device which can reduce the current consumption when it is on standby by removing a system clock signal which is to be input to a circuit for detecting the level of a clock activation signal CKE, and (2) providing a synchronous semiconductor storage device which can reduce the current consumption, even when in operation, as long as it operates in a clock suspension mode.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.